In a portable electronic apparatus, a battery pack which is easily handled is wide used. The battery pack stores one or a plurality of secondary batteries in one package. As the secondary battery, one having a large capacity, such as a lithium ion battery, a lithium polymer battery, a nickel hydrogen battery, or such, is used. The large capacity battery has very large energy therein, and thus, it may heat, or in some case, it may burn, when overcharge, overdischarge, overcurrent or such occurs.
Therefore, a semiconductor unit for protecting the secondary battery is provided inside of the battery pack, for protecting the secondary battery from overcharge, overdischarge, charging overcurrent, discharging overcurrent, short circuit current or such, whereby, if actual protection is necessary, the semiconductor unit breaks connection between the secondary battery and a charger or a load apparatus, and thus, heating and burning is prevented.
The semiconductor unit for protecting the secondary battery has a special detecting circuit for detecting each of overcharge, overdischarge, charging overcurrent, discharging overcurrent, short circuit current and so forth. The detecting circuit outputs a detection signal when detecting such abnormality as that requiring protecting operation, turns off a switch device to break connection between the secondary battery and a charger or a load apparatus
However, if a configuration is provided such that the switch device is immediately turned off when the detection signal is output, power supply to the load apparatus may be interrupted even by output of the detection signal which is merely within a very short time due to malfunction caused by noise or such, whereby a problem may occur such that the load apparatus may cause malfunction or such accordingly. In order to prevent such malfunction, commonly a configuration is provided such that determination is made that true abnormality has occurred only when abnormality continues even after a predetermined time has elapsed since the detection signal was output, and then, the switch device is turned off.
The above-mentioned predetermined time is called a ‘delay time’. As the delay time, a different time (in a range between tens of milliseconds and seconds) is set depending on the particular contents of the abnormality detected. That is, the delay time is set shorter as the detected abnormality is of a higher degree or requires urgency. On the other hand, the delay time is set longer as the detected abnormality is of a lower degree or does not require urgency.
For example, the delay time for detecting overdischarge is on the order of 16 milliseconds, the delay time for detecting overcurrent is on the order of 10 milliseconds, the delay time for detecting short circuit is on the order of 1 millisecond. On the other hand, the delay time for detecting overcharge by means of an overcharge detecting circuit is equal to or larger than 1 second, or, at longest, it may be on the order of 5 seconds.
However, if the above-mentioned delay time should be waited for when such a semiconductor unit for protection a secondly battery is tested in an occasion of characteristic inspection, shipping inspection or such, the inspection requires a too long time, thus mass production effect may degrade, and thus, the cost may increase.
For the purpose of solving the problem, when such a semiconductor unit is tested, a test signal is applied to the semiconductor unit, whereby the delay time is shortened and thus, the test time is shortened. However, since such a semiconductor unit for protecting a secondary battery should be accommodated by a battery pack, it should be miniaturized. From this viewpoint, it is necessary to avoid such a situation that, one pin is added to provide a test terminal for the test signal, whereby an existing small package cannot accommodate the semiconductor unit and a larger package should be prepared therefor, or, the number of bonding pads increases for the test terminal, an IC chip size increases and thus, an extra space or an extra cost may arise.
Japanese Laid-Open Patent Application 2005-12852 discloses an art proposed by the present applicant, for the purpose of solving the above-mentioned problem. FIG. 6 shows a block diagram of a battery pack disclosed therein.
As shown in FIG. 6, the battery pack 20 includes a semiconductor unit 1 for protecting a secondary battery (in FIG. 6, an internal configuration is not shown), the secondary battery 21, a discharge control NMOS transistor M21, a charge control NMOS transistor M22, a capacitor C21 and resistors R21 and R22, and has a plus terminal 22 and a minus terminal 23. To the plus terminal 22 and the minus terminal 23, a charger 30 (when the secondary battery 21 is charged) or a load apparatus 30 (when the secondary battery 21 is discharged) is connected.
The semiconductor unit 1 has a current detecting terminal V− for detecting a discharging overcurrent or a charging overcurrent. A voltage of the current detecting terminal V− with respect to a terminal Vss is a plus voltage upon discharging and is a minus voltage upon charging.
In the art disclosed by Japanese Laid-Open Patent Application 2005-12852, such a function is provided that, when a negative voltage, lower than a negative voltage occurring from a normal charging overcurrent, is applied to the current detecting terminal V−, the delay time is reduced. Thereby, the above-mentioned test terminal required in the above-mentioned prior art can be omitted, and thus, it is possible to avoid increase in the package size and increases in the chip size.
A delay circuit provided in the semiconductor unit 1 has an oscillating circuit shown in FIG. 8, and a counter circuit for counting clock pulses of a clock signal CLK generated by the oscillating circuit. The oscillating circuit is a ring oscillating circuit including inverter circuits 41 through 45 as shown in FIG. 8.
Setting of an oscillation frequency in the ring oscillating circuit utilize times required for charging/discharging capacitors C1 and C2 at the outputs of the constant current inverters 41 and 44. The oscillation frequency of the ring oscillating circuit can be increased as a result of constant current values from constant current sources I1 through I4 of the constant current inverters 41 and 44 being substantially increased. In a test mode, the oscillation frequency of the oscillating circuit is increased as a result of the constant current values applied to the constant current inverters 41 and 44 being increased, and thus, the delay time is shortened accordingly. Below, specific operation thereof will be described with reference to FIG. 8.
In regular operation, a test signal TEST has a high level, and PMOS transistors M1 and M2 are turned off. Thereby, currents from current sources I3 and I4 are not supplied to the constant current inverters 41 and 44, and thus, charging/discharging of the capacitors C1 and C2 is carried out only by the constant current sources I1 and I2. As a result, times for the charging/discharging increase, and thus, the oscillation frequency lowers.
In contrast thereto, in a testing occasion, a low level is applied to the test signal TEST, and thus, the PMOS transistors M1 and M2 are turned on. Thereby, currents from the constant current sources I3 and I4 are also supplied to the constant current inverters 41 and 44. As a result, charging/discharging of the capacitor C1 is carried out by a sum current of the currents from the constant current sources I1 and I3. In the same manner, charging/discharging of the capacitor C2 is carried out by a sum current of the currents from the constant current sources I2 and I4. As a result, times required for charging/discharging the capacitors C1 and C2 are shortened, and thus, the oscillation frequency increases. As a result, the delay time is shortened as mentioned above.
However, for the oscillating circuit, the frequency of the clock signal may not be accurately set. This is because, due to process variation, the current values of the constant current sources 11 through 14, and capacitances of the capacitors C1 and C2 may vary.
Further, a ratio between the oscillation frequency in the testing occasion and the oscillation frequency in the regular operation may have process variation. When this ratio is increased, the variation in the ratio increases accordingly. As a result, the ratio between the low clock frequency in the regular operation and the high clock frequency in the testing occasion may not be set accurately, and thus, in the test with the use of the high clock frequency, a test time may vary for each product of the semiconductor unit.
In order to solve the problem, the present applicant proposed an improved counter circuit (in Japanese Patent Application No. 2006-245021) as shown in FIG. 7. This counter circuit 12 shows in FIG. 7 has such a configuration that a plurality of flip-flop circuits FF1 through FFn are connected in a cascade manner for inputting the clock signal CLK and counting the number of clock pulses. A signal inverted from an output of a flip-flop circuit in the last stage or a predetermined stage of the counter circuit 12 is used as a delay time signal. Also, in a testing occasion for the semiconductor unit with using this delay circuit (i.e., when the first test signal TEST1 is in the low level, which means an active state, i.e., low active or negative logic), the delay time generated with the use of an output signal from a flip-flop circuit in the first stage or a stage close to the first stage is used. Thus, the delay time can be shortened. As a result, it is possible to shorten the delay time without increasing the oscillation frequency.
However, in the circuit of FIG. 7, in the testing occasion, since only the flip-flop circuits up to those used for generating the above-mentioned shortened delay time are used, it is necessary to separately carry out a test as to whether or not the flip-flop circuits subsequent thereto operate properly.
For this purpose, operation check of all the flip-flop circuits FF1 through FFn of the counter circuit 12 of the delay circuit is carried out within a reduced time, as a result of, in response to another test signal (referred to as a second test signal TEST2) than the first test signal TEST1, the oscillation frequency of the oscillation circuit being increased, as described above with reference to FIG. 8. That is, in this case, as the test signal TEST shown in FIG. 8, the above-mentioned second test signal TEST2 is applied.
That is, for example, when the entire semiconductor unit 1 including the delay circuit (including the counter circuit 12 and the oscillating circuit 13) is tested, the first test signal TEST1 may be made active (i.e., to have the low level) with the second test signal TEST2 non-active (i.e., to have a high level), while, when particularly the delay circuit (including the counter circuit 12 and the oscillating circuit 13) is tested, the second test signal TEST2 may be made active (i.e., to have the low level) with the first test signal TEST1 non-active (i.e., to have the high level).
Thereby, when the entire semiconductor unit 1 is tested, the oscillating circuit 13 operates with the normal oscillation frequency, and the counter circuit 12 generates the shortened delay time as a result of the output of the flip-flop circuit in the first stage or the predetermined stage close thereto being used as mentioned above. On the other hand, when particularly the delay circuit is tested, the oscillating circuit 13 operates with the increased oscillation frequency as a result of the charging/discharging currents being increased as mentioned above, and the counter circuit 12 uses the output of the flip-flop circuit in the last stage or the predetermined stage as mentioned above whereby all the flip-flop circuits FF1 through FFn can be tested at once in this case.
However, as mentioned above, adding a new terminal for applying the second test signal TEST2 to the semiconductor unit 1 is not preferable from a viewpoint of miniaturization.